1) Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to a method of combining PLDD (p-type lightly doped drain) implant and surface implant for ROM cell surface implant region to reduce processing steps and simplify the process.
2) Description of the Prior Art
Currently, CMOS ROM cells require numerous photolithograpy and implant steps for NLDD (n-type lightly doped source and drain regions), PLDD (p-type lightly doped source and drain regions), n-type and p-type source and drain region implants, and surface implants for ROM cell surface implant region. These photolithography and implant steps add cost and processing time as well as increasing opportunities for loss Is of cells due to processing variations. A need exists to reduce the number of processing steps, thereby reducing cost and processing time and improving process yield.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,538,914 (Chiu et al.) teaches a LDD method for a ROM.
U.S. Pat. No. 5,700,729 (Lee et al.) discloses a masked gate MOS source and drain ion implant method including a PLDD.
U.S. Pat. No. 5,830,795 (Mehta et al.) recites a simplified masking process for a logic device including PLDD and Vt ion implant steps.
U.S. Pat. No. 5,843,816 (Liaw et al.) shows a process for a SRAM using a PLDD implant step.
U.S. Pat. No. 5,650,341 (Yang et al.) teaches a method for forming a CMOS PLDD and NLDD using a method to reduce masking steps and costs.